Fully depleted silicon-on-insulator (FDSOI) with a gate first processing utilizes a continuous shallow trench isolation (STI) dummy gate tie down to voltage drain drain (VDD) to form circuit isolation on p-channel field-effect transistor (PFET), due to a lightly doped drain (LDD) drop from silicon germanium (SiGe) strain relaxation at the STI region edge. This OFF device introduces higher leakage compared to a physical diffusion break. In addition, area is lost due to the need for filler cells that separate drain/drain abutment. An active layer filler, such as a STI, is needed to insert voltage source source (VSS) between two separate drains which decreases available area.
A need therefore exists for devices and related method to provide dummy gate isolation with a physical active layer cut which avoids the continuous active layer filler for gate first FDSOI.